Altium

Design Rule Verification Report

Date: 2017/11/6
Time: 22:33:58
Elapsed Time: 00:00:01
Filename: F:\AD_Prj\Now\Project\Smart_Belt\Verification\Res_Measure\Res_Measure.PcbDoc
Warnings: 0
Rule Violations: 77

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=15mil) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 1
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=15mil) (Max=50mil) (Preferred=20mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 4
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All) 4
Silk To Solder Mask (Clearance=10mil) (IsPad),(All) 64
Silk to Silk (Clearance=10mil) (All),(All) 4
Net Antennae (Tolerance=0mil) (All) 0
Room Res_Measure (Bounding Region = (890.433mil, 955mil, 7055mil, 5070mil) (InComponentClass('Res_Measure')) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total 77

Un-Routed Net Constraint ( (All) )
Un-Routed Net Constraint: Net GND Between Pad P5-1(4105mil,3340mil) on Multi-Layer And Pad Free-1(4800mil,3350mil) on Multi-Layer

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Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Hole Size Constraint: (118.11mil > 100mil) Pad Free-4(3250mil,3350mil) on Multi-Layer Actual Hole Size = 118.11mil
Hole Size Constraint: (118.11mil > 100mil) Pad Free-3(3250mil,2850mil) on Multi-Layer Actual Hole Size = 118.11mil
Hole Size Constraint: (118.11mil > 100mil) Pad Free-2(4800mil,2850mil) on Multi-Layer Actual Hole Size = 118.11mil
Hole Size Constraint: (118.11mil > 100mil) Pad Free-1(4800mil,3350mil) on Multi-Layer Actual Hole Size = 118.11mil

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Minimum Solder Mask Sliver (Gap=10mil) (All),(All)
Minimum Solder Mask Sliver Constraint: (6.882mil < 10mil) Between Pad C3-1(4260.433mil,3205mil) on Top Layer And Pad C2-1(4259.567mil,3275mil) on Top Layer [Top Solder] Mask Sliver [6.882mil]
Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad P4-2(4615mil,3080mil) on Multi-Layer And Pad P4-1(4615mil,2980mil) on Multi-Layer [Top Solder] Mask Sliver [7mil] / [Bottom Solder] Mask Sliver [7mil]
Minimum Solder Mask Sliver Constraint: (8.5mil < 10mil) Between Pad P3-2(3690mil,2990mil) on Multi-Layer And Pad P3-1(3690mil,3090mil) on Multi-Layer [Top Solder] Mask Sliver [8.5mil] / [Bottom Solder] Mask Sliver [8.5mil]
Minimum Solder Mask Sliver Constraint: (7mil < 10mil) Between Pad P5-2(4005mil,3340mil) on Multi-Layer And Pad P5-1(4105mil,3340mil) on Multi-Layer [Top Solder] Mask Sliver [7mil] / [Bottom Solder] Mask Sliver [7mil]

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Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4406.378mil,2875mil)(4453.622mil,2875mil) on Top Overlay And Pad R14-1(4430mil,2839.567mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4406.378mil,2875mil)(4453.622mil,2875mil) on Top Overlay And Pad R14-2(4430mil,2910.433mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Text "R4" (4455mil,2924.567mil) on Top Overlay And Pad R14-2(4430mil,2910.433mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4491.378mil,2875mil)(4538.622mil,2875mil) on Top Overlay And Pad R13-1(4515mil,2910.433mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4491.378mil,2875mil)(4538.622mil,2875mil) on Top Overlay And Pad R13-2(4515mil,2839.567mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4336.378mil,3075mil)(4383.622mil,3075mil) on Top Overlay And Pad R6-1(4360mil,3039.567mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4336.378mil,3075mil)(4383.622mil,3075mil) on Top Overlay And Pad R6-2(4360mil,3110.433mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4475.433mil,3016.378mil)(4475.433mil,3063.622mil) on Top Overlay And Pad R9-1(4440mil,3040mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4475.433mil,3016.378mil)(4475.433mil,3063.622mil) on Top Overlay And Pad R9-2(4510.866mil,3040mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4236.378mil,2874.567mil)(4283.622mil,2874.567mil) on Top Overlay And Pad C1-1(4260mil,2910mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4236.378mil,2874.567mil)(4283.622mil,2874.567mil) on Top Overlay And Pad C1-2(4260mil,2839.134mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4295mil,3251.378mil)(4295mil,3298.622mil) on Top Overlay And Pad C2-1(4259.567mil,3275mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4295mil,3251.378mil)(4295mil,3298.622mil) on Top Overlay And Pad C2-2(4330.433mil,3275mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (4.745mil < 10mil) Between Text "C3" (4305mil,3210mil) on Top Overlay And Pad C2-2(4330.433mil,3275mil) on Top Layer [Top Overlay] to [Top Solder] clearance [4.745mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4225mil,3181.378mil)(4225mil,3228.622mil) on Top Overlay And Pad C3-1(4260.433mil,3205mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4225mil,3181.378mil)(4225mil,3228.622mil) on Top Overlay And Pad C3-2(4189.567mil,3205mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4321.378mil,2875mil)(4368.622mil,2875mil) on Top Overlay And Pad R4-1(4345mil,2910.433mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (4321.378mil,2875mil)(4368.622mil,2875mil) on Top Overlay And Pad R4-2(4345mil,2839.567mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3861.378mil,3340.433mil)(3908.622mil,3340.433mil) on Top Overlay And Pad C4-1(3885mil,3305mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3861.378mil,3340.433mil)(3908.622mil,3340.433mil) on Top Overlay And Pad C4-2(3885mil,3375.866mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3776.378mil,3125.433mil)(3823.622mil,3125.433mil) on Top Overlay And Pad R1-1(3800mil,3090mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3776.378mil,3125.433mil)(3823.622mil,3125.433mil) on Top Overlay And Pad R1-2(3800mil,3160.866mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3776.378mil,3270.433mil)(3823.622mil,3270.433mil) on Top Overlay And Pad R2-1(3800mil,3235mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3776.378mil,3270.433mil)(3823.622mil,3270.433mil) on Top Overlay And Pad R2-2(3800mil,3305.866mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (9.941mil < 10mil) Between Track (3860mil,2840mil)(3860mil,2900mil) on Top Overlay And Pad R10-1(3880.433mil,2940mil) on Top Layer [Top Overlay] to [Top Solder] clearance [9.941mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3845mil,2916.378mil)(3845mil,2963.622mil) on Top Overlay And Pad R10-1(3880.433mil,2940mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3845mil,2916.378mil)(3845mil,2963.622mil) on Top Overlay And Pad R10-2(3809.567mil,2940mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3920.433mil,3206.378mil)(3920.433mil,3253.622mil) on Top Overlay And Pad R11-1(3955.866mil,3230mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3920.433mil,3206.378mil)(3920.433mil,3253.622mil) on Top Overlay And Pad R11-2(3885mil,3230mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3861.378mil,3125mil)(3908.622mil,3125mil) on Top Overlay And Pad R7-1(3885mil,3089.567mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3861.378mil,3125mil)(3908.622mil,3125mil) on Top Overlay And Pad R7-2(3885mil,3160.433mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3946.378mil,3125mil)(3993.622mil,3125mil) on Top Overlay And Pad R8-1(3970mil,3089.567mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3946.378mil,3125mil)(3993.622mil,3125mil) on Top Overlay And Pad R8-2(3970mil,3160.433mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3946.378mil,2979.567mil)(3993.622mil,2979.567mil) on Top Overlay And Pad R3-1(3970mil,2944.134mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3946.378mil,2979.567mil)(3993.622mil,2979.567mil) on Top Overlay And Pad R3-2(3970mil,3015mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3845.433mil,2991.378mil)(3845.433mil,3038.622mil) on Top Overlay And Pad R5-1(3880.866mil,3015mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3845.433mil,2991.378mil)(3845.433mil,3038.622mil) on Top Overlay And Pad R5-2(3810mil,3015mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (3.878mil < 10mil) Between Track (3760mil,2985mil)(3780mil,3005mil) on Top Overlay And Pad R5-2(3810mil,3015mil) on Top Layer [Top Overlay] to [Top Solder] clearance [3.878mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3617.008mil,3359.213mil)(3617.008mil,3414.331mil) on Top Overlay And Pad D1-1(3680mil,3463.543mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3742.992mil,3359.213mil)(3742.992mil,3414.331mil) on Top Overlay And Pad D1-1(3680mil,3463.543mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (4.389mil < 10mil) Between Text "R12" (3531mil,3436mil) on Top Overlay And Pad D1-1(3680mil,3463.543mil) on Top Layer [Top Overlay] to [Top Solder] clearance [4.389mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3617.008mil,3359.213mil)(3617.008mil,3414.331mil) on Top Overlay And Pad D1-2(3680mil,3310mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3742.992mil,3359.213mil)(3742.992mil,3414.331mil) on Top Overlay And Pad D1-2(3680mil,3310mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3617.008mil,3359.213mil)(3742.992mil,3359.213mil) on Top Overlay And Pad D1-2(3680mil,3310mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3541.378mil,3340.433mil)(3588.622mil,3340.433mil) on Top Overlay And Pad R12-1(3565mil,3375.866mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3541.378mil,3340.433mil)(3588.622mil,3340.433mil) on Top Overlay And Pad R12-2(3565mil,3305mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3456.378mil,3340.433mil)(3503.622mil,3340.433mil) on Top Overlay And Pad D2-1(3480mil,3375.866mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Track (3456.378mil,3340.433mil)(3503.622mil,3340.433mil) on Top Overlay And Pad D2-2(3480mil,3305mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (4614.252mil,2931.575mil)(4614.252mil,3128.425mil) on Top Overlay And Pad P4-1(4615mil,2980mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (0.898mil < 10mil) Between Text "R9" (4585mil,3015mil) on Top Overlay And Pad P4-1(4615mil,2980mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0.898mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (4614.252mil,2931.575mil)(5145.748mil,2931.575mil) on Top Overlay And Pad P4-1(4615mil,2980mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (4614.252mil,2931.575mil)(4614.252mil,3128.425mil) on Top Overlay And Pad P4-2(4615mil,3080mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Text "R9" (4585mil,3015mil) on Top Overlay And Pad P4-2(4615mil,3080mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (4614.252mil,3128.425mil)(5145.748mil,3128.425mil) on Top Overlay And Pad P4-2(4615mil,3080mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (3690.748mil,2941.575mil)(3690.748mil,3138.425mil) on Top Overlay And Pad P3-1(3690mil,3090mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (3159.252mil,3138.425mil)(3690.748mil,3138.425mil) on Top Overlay And Pad P3-1(3690mil,3090mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (3690.748mil,2941.575mil)(3690.748mil,3138.425mil) on Top Overlay And Pad P3-2(3690mil,2990mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (7.743mil < 10mil) Between Track (3760mil,2985mil)(3780mil,3005mil) on Top Overlay And Pad P3-2(3690mil,2990mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [7.743mil]
Silk To Solder Mask Clearance Constraint: (7.743mil < 10mil) Between Track (3760mil,2870mil)(3760mil,2985mil) on Top Overlay And Pad P3-2(3690mil,2990mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [7.743mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (3159.252mil,2941.575mil)(3690.748mil,2941.575mil) on Top Overlay And Pad P3-2(3690mil,2990mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (3956.575mil,3339.252mil)(4153.425mil,3339.252mil) on Top Overlay And Pad P5-1(4105mil,3340mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (4153.425mil,3339.252mil)(4153.425mil,3870.748mil) on Top Overlay And Pad P5-1(4105mil,3340mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (3956.575mil,3339.252mil)(3956.575mil,3870.748mil) on Top Overlay And Pad P5-2(4005mil,3340mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 10mil) Between Track (3956.575mil,3339.252mil)(4153.425mil,3339.252mil) on Top Overlay And Pad P5-2(4005mil,3340mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [0mil]

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Silk to Silk (Clearance=10mil) (All),(All)
Silk To Silk Clearance Constraint: (5mil < 10mil) Between Text "R5" (3785mil,2840mil) on Top Overlay And Track (3760mil,2870mil)(3775mil,2855mil) on Top Overlay Silk Text to Silk Clearance [5mil]
Silk To Silk Clearance Constraint: (8.996mil < 10mil) Between Text "U1" (4145mil,3040mil) on Top Overlay And Track (4129.567mil,2956.575mil)(4129.567mil,3153.425mil) on Top Overlay Silk Text to Silk Clearance [8.996mil]
Silk To Silk Clearance Constraint: (9.009mil < 10mil) Between Text "U1" (4145mil,3040mil) on Top Overlay And Track (4200.433mil,2956.575mil)(4200.433mil,3153.425mil) on Top Overlay Silk Text to Silk Clearance [9.009mil]
Silk To Silk Clearance Constraint: (4.01mil < 10mil) Between Text "C3" (4305mil,3210mil) on Top Overlay And Text "R6" (4326mil,3171mil) on Top Overlay Silk Text to Silk Clearance [4.01mil]

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